Assertion to check for the pulses of the clock

SystemVerilog
11

In reply to Lina.Lin:

Hi lina/Ben

As per my understanding,

The first line @(posedge sample_clk) disable iff (reset || scan_en) says

Disable the assertion if there is a reset or scan_en==1 and it will go to next line only when reset ==0 and scan_en==0 but when scan_en == 1’b0 there will not be any sample_clk.

The only clock I can see when scan_en==0 is func_clk.

Now my question is how it will go to second line since there will not be a sample clk when scan_en==0.

Thanks
durga