Assertion to check for the pulses of the clock

SystemVerilog
10

In reply to ben@SystemVerilog.us:

Thanks Ben. multi-clocking assertion works much better and simpler.


   property P_CHECK_MULTI_CLOCKING;
     realtime t; 
     @(posedge sample_clk) disable iff (reset||scan_en) 
     $fell(scan_en) |-> @(posedge func_clk)  (1, t=$realtime) ##1 (($realtime-t)== FUNC_CLK_PERIOD);    
   endproperty