In reply to ben@SystemVerilog.us:
Hi Ben ,
Honestly speaking I didn’t get the question.When I went through this question , I thought the following one could be one of the possible ways.
property check;
@(posedge clk150) strong(a) |-> (clk != $past(clk,1));
endproperty
Then I noticed that the operation cannot be done with respect to clk150, couldn’t understand why?
Now there are only two signals we can take into our consideration : signal-a and signal-clk. I am trying to make the signal-a reference signal.
property check;
@(posedge a) (clk!=$past(clk,1));
endproperty
Hope this one makes something meaningful.