Assertion to check clock toggling

SystemVerilog
,
3

In reply to TRUSHAL:

// create an event to detect when signal 'a' goes high
event a_high;
always @(a) begin
    if (a) a_high = 1;
end

// create an event to detect when 'clk' changes
event clk_changed;
always @(posedge clk) clk_changed = 1;

// create an assertion to check that 'clk' toggles when 'a' is high
always @(a_high or clk_changed) begin
    if (a_high)
        assert(clk_changed) else $error("clk did not toggle when a was high");
end

// Create an assertion to check that clk150 has a frequency of 150 MHz
property freq150;
    (clk150) |-> freq150;
    freq150 = #1 (clk150);
endproperty

always @(posedge clk150) begin
    assert(freq150==150MHz) else $error("clk150 does not have a frequency of 150MHz");
end