Assertion to check clock is disabled

SystemVerilog
,
1

Hi All ,
I have a requirement that whenever signal ’ iso_en ’ is sampled true on sys_clk , after 1 clock there should be no ip_clk i.e no edge of ip_clk .
Later if iso_en again changes from true ( 1 ) → false ( 0 ) , ip_clk would start re-running .

So my first attempt was as follows :


//  Attempt1 
property  clk_disable ;
 @( posedge sys_clk )   iso_en  |=>   ! ip_clk  ;
endproperty
assert  property ( clk_disable );

This however has a limitation :
After iso_en is True , even if the ip_clk is running and the posedge of ip_clk and sys_clk overlaps then the preponed value of 0 will be sampled and no error would be flashed !!

So then my 2nd attempt was as follows : edalink_attempt2

This however has a limitation that the threads which are waiting for change in ’ op_ip_clk ’ in Consequent and
iso_en changes from true to false the ip_clk would re-run and the threads that are waiting for @( op_ip_clk ) would result in assertion failure !!

I need a logic to ensure that assertion passes if ’ iso_en ’ transitions later from 1 to 0 and there is no change in ’ op_ip_clk ’ up till then .
Any suggestions ?

Unfortunately the following doesn’t work , maybe since LHS of throughout can’t be Temporal :


//  Attempt3 
 sequence  through_out ;
    !( @( op_ip_clk ) )  throughout  ( $fell( iso_en ) [->1] ) 
  endsequence

  property  clk_check ;
    @(  posedge  op_sys_clk  )  iso_en  |=>  ##1 (  through_out   ) ;
  endproperty
2

In reply to Have_A_Doubt:
I am not familiar with the timing of this interface, so I’ll give a suggestion.
Consider the use of tasks to do what you need.
I demonstrate that in To check clock toggling - SystemVerilog - Verification Academy
code https://www.edaplayground.com/x/gK3M
You can fire the task with something like

@( posedge sys_clk )   iso_en  |-> (1, my_task(v1, v2, ..);// v1, v2, are sampled values. 
task automatic mYtask(bit a, b, ..); 
  @(posedge ..) ... 
  am_is0: assert #0(ip_clk==0); // guessing on the ip_clk

The task gives you more flexibilities than SVA as you have all the power of SV.

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Cohen_Links_to_papers_books - Google Docs

Getting started with verification with SystemVerilog

3

In reply to ben@SystemVerilog.us:

Thanks Ben ,
Will look into the link .

One quick thought , adding disable iff could work as well :


property  clk_check ;

   @(  posedge  op_sys_clk  )  disable iff ( ! iso_en ) 
   
                               iso_en  |=>  ##1  @( op_ip_clk )  0 ;  

 endproperty

So threads that are waiting for change in ’ op_ip_clk ’ in consequent ( as soon as iso_en is de-asserted ) would be disabled .
As a result there would be No Error Messages as initially observed in edalink_attempt2

4

In reply to Have_A_Doubt:

You’re disabling the property with iso_en==0, thus the only assertions that start are those with iso_en==1. If iso_en==1 for 3 cycles, and then iso_en==1, and if each assertion last 4 cycle (as an example), then the only assertion that still stands is the one with the most recent iso_en==1. The others are canceled. Is this what you want?
It’s unusual to do this. You typically define what you want or expect in an assertion.