Assertion to calculate ON and OFF period of signal based on the configuration

SystemVerilog
,
5

In reply to muralidar:
Did another run and am showing sim results. I believe it would be safer to cast the realtime to unsigned when doing comparisons. Thus

vthi=int'(vt_hi);  // Casting needed? Better practice!
vthi=unsigned'(vthi); // Needed?

I did a simulation run with and without the unsigned casting and got the same results, but I believe tht it would be better practice to make the casting. From my Real Chip book:
“An object of type reg is processed by Verilog as an UNSIGNED number, however, it can be assigned a negative constant. Negative numbers are represented in 2’s complement form. A reg object loses the significance of the SIGN bit. An object of type integer is processed by Verilog as a SIGNED number and retains the significance of the sign. The difference between SIGNED and UNSIGNED number is in SIGN or ZERO extension of the left most bits when arithmetic and logical operations are performed. Section 4.4.1 of the Verilog LRM specifies the rules for expression bit lengths. For “+ - / % & | ^ ^~ ~^” arithmetic operations, and for “=== !== == != && || > >= < <=” logical operations, the number of bits used in the expression evaluations is the maximum of the length of the left operand and the right operand. Remember that an integer value is a 32-bit value, whereas a sized value is defined by the value of the size. Decimal numbers are signed. Based-numbers (e.g., 4’h21) are unsigned. An UNSIZED value (e.g., 'h5) is 32 bits. Unsized unsigned constants, where the high order bit is unknown (e.g., X or x) or tri-state (Z or z), are extended to the size of the expression containing the constant. If the size of the unsigned number is smaller than the size specified for the constant (e.g. intA32bits = 'hF;), the unsigned number is padded to the left with zeros (e.g., intA32bits = 32’h0000_000F;). If the leftmost bit in the unsigned number is an x or a z, then an x or a z is used to pad to the left respectively.”


import uvm_pkg::*; `include "uvm_macros.svh" 
module TB;
  bit clk, A;
  // default clocking @(posedge clk); endclocking
  initial forever #10 clk=!clk;  
  bit[3:0] cnt;
  int v_t, v_t_hi;
  bit [31:0] cnt_reg_1=32'H12345678;
  bit [31:0] cnt_reg_2=32'H9ABCDEF0;
     
    function void check_cnt(realtime vt_hi); 
    	automatic int vthi;
    	vthi=int'(vt_hi);  // Casting needed? Better practice!
    	vthi=unsigned'(vthi); // Needed? 
    	cnt++; $display("@t= %t, cnt=%d, vthi=%d", $time, cnt, vthi); // debug  
    	if(cnt ==0) 
    		a0: assert(vthi == cnt_reg_1[11:0]);
    	if(cnt == 1)
    		a1: assert(vthi == cnt_reg_1[23:12]);
    	if(cnt ==2)
    		a2: assert(vthi == cnt_reg_2[11:0]);
    	if(cnt ==3)
    		a3: assert(vthi == cnt_reg_2[23:12]);		 	 
    endfunction : check_cnt  
	
    property p_width; 
    	realtime  v_t, v_t_hi;
    	@(posedge A) (1, v_t    = $realtime)  ##0 	
    	@(negedge A) (1, v_t_hi = $realtime-v_t, check_cnt(v_t_hi));	
    endproperty 
    cover property(p_width); 
	
    initial begin 
    	repeat(200) begin 
    		@(posedge clk);   
    		if (!randomize(A)  with 
    				{ A dist {1'b1:=3, 1'b0:=1};
    				}) `uvm_error("MYERR", "This is a randomize error")
    				end 
    		$stop; 
    end  	
endmodule 
@t=                   30, cnt= 1, vthi=         20
# ** Error: Assertion error.
#    Time: 30 ns  Scope: TB.check_cnt.a1 File: width.sv Line: 22
# @t=                  330, cnt= 2, vthi=        280
# ** Error: Assertion error.
#    Time: 330 ns  Scope: TB.check_cnt.a2 File: width.sv Line: 24
# @t=                  410, cnt= 3, vthi=         60
# ** Error: Assertion error.
#    Time: 410 ns  Scope: TB.check_cnt.a3 File: width.sv Line: 26
# @t=                  510, cnt= 4, vthi=         80
# @t=                  750, cnt= 5, vthi=        200
# @t=                  790, cnt= 6, vthi=         20
# @t=                  870, cnt= 7, vthi=         60
# @t=                  930, cnt= 8, vthi=         40
# @t=                  970, cnt= 9, vthi=         20
# @t=                 1010, cnt=10, vthi=         20
# @t=                 1130, cnt=11, vthi=        100
# @t=                 1210, cnt=12, vthi=         60
# @t=                 1290, cnt=13, vthi=         60
# @t=                 1350, cnt=14, vthi=         40
# @t=                 1490, cnt=15, vthi=        100
# @t=                 1730, cnt= 0, vthi=        220
# ** Error: Assertion error.
#    Time: 1730 ns  Scope: TB.check_cnt.a0 File: width.sv Line: 20
# @t=                 1850, cnt= 1, vthi=        100
# ** Error: Assertion error.
#    Time: 1850 ns  Scope: TB.check_cnt.a1 File: width.sv Line: 22
# @t=                 1990, cnt= 2, vthi=         60
# ** Error: Assertion error.
#    Time: 1990 ns  Scope: TB.check_cnt.a2 File: width.sv Line: 24
# @t=                 2150, cnt= 3, vthi=        140
# ** Error: Assertion error.
#    Time: 2150 ns  Scope: TB.check_cnt.a3 File: width.sv Line: 26
# @t=                 2290, cnt= 4, vthi=        120
# @t=                 2490, cnt= 5, vthi=        180
# @t=                 2550, cnt= 6, vthi=         40
# @t=                 2690, cnt= 7, vthi=        120
# @t=                 2750, cnt= 8, vthi=         20
# @t=                 2910, cnt= 9, vthi=        140

Ben Cohen
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