Assertion to calculate ON and OFF period of signal based on the configuration

SystemVerilog
,
4

In reply to muralidar:
I used your model as a guideline. Usually, in assertions, clocks are used to sample signals. You used events on A, instead of sampling A based on a clock.
The model I wrote seems to do what you want. I used the sequence_match_item with a function call to do the last calculations. Also, realtime is real, the count is integer. I did a type cast.


/*I need to calculate the width of the particular pulse of signal A and 
should compare with the particular register based on cnt no.so here cnt_no can be 1 to 32;
Please help how can i write generic assertion code for this. */ 
import uvm_pkg::*; `include "uvm_macros.svh" 
module TB;
  bit clk, A;
  // default clocking @(posedge clk); endclocking
  initial forever #10 clk=!clk;  
  bit[3:0] cnt;
  int v_t, v_t_hi;
  bit [31:0] cnt_reg_1=32'H12345678;
  bit [31:0] cnt_reg_2=32'H9ABCDEF0;
     
    function void check_cnt(realtime vt_hi); 
    	automatic int vthi;
    	vthi=int'(vt_hi);  // Casting needed? Better practice!
    	cnt++; 
    	if(cnt ==0) 
    		a0: assert(vthi == cnt_reg_1[11:0]);
    	if(cnt == 1)
    		a1: assert(vthi == cnt_reg_1[23:12]);
    	if(cnt ==2)
    		a2: assert(vthi == cnt_reg_2[11:0]);
    	if(cnt ==3)
    		a3: assert(vthi == cnt_reg_2[23:12]);		 	 
    endfunction : check_cnt  
	
    property p_width; 
    	realtime  v_t, v_t_hi;
    	@(posedge A) (1, v_t    = $realtime)  ##0 	
    	@(negedge A) (1, v_t_hi = $realtime-v_t, check_cnt(v_t_hi));	
    endproperty 
    cover property(p_width); 
	
    initial begin 
    	repeat(200) begin 
    		@(posedge clk);   
    		if (!randomize(A)  with 
    				{ A dist {1'b1:=1, 1'b0:=3};
    				}) `uvm_error("MYERR", "This is a randomize error")
    				end 
    		$stop; 
    end  	
endmodule

Ben Cohen
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