Assertion to calculate ON and OFF period of signal based on the configuration

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Hi Ben,
Below is my sample SV code for my requirement.
I need to calculate the width of the particular pulse of signal A and should compare with the particular register based on cnt no.so here cnt_no can be 1 to 32;
Please help how can i write generic assertion code for this.

module TB;
int bit[3:0] cnt;
int v_t, v_t_hi;
bit [31:0] cnt_reg_1;
bit [31:0] cnt_reg_2;
always @(posedge A) begin
v_t = $realtime;

@(negedge A) 
v_t_hi = $realtime-v_t;
cnt++;
if(cnt ==0) 

if (v_t_hi == cnt_reg_1[11:0])
 begin
 $display("Error in matching reg value");
end
if(cnt == 1)
if(v_t_hi == cnt_reg_1[12:23])
 begin
 $display("Error in matching reg value");
end
if(cnt ==2)
if (v_t_hi == cnt_reg_2[11:0]) begin
 $display("Error in matching reg value");
end
if(cnt ==3)
if(v_t_hi == cnt_reg_2[12:23]) begin
 $display("Error in matching reg value");
end
end

endmodule

Please help.