In reply to muralidar:
Keep in mind that an assertion is a statement that a property is true. SVA is just a notation / language that facilitates the coding. When you say “whereas in SV feels easy”, I suggest that you use SV, probably with concurrent tasks if you want to emulate concurrency.
I failed to fully understand your requirements. If you show your SV code, I maybe able to translate it to SVA.
Ben Cohen
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- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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