Assertion signal low between two other ones

UVM
,
1

Hi all
I’m trying to assert that a signal remains low between two others signal

assert property (@(posedge clk) disable iff (!reset_n) (a |=> (!c) throughout (b [-> 1])))

this code doesn’t work because c is evaluated also when b = 1

Any kind of help will be appreciated.
Thanks

2

Seems like this question is more of an SV Forum question rather than a UVM one. If I understand you, maybe something like:

( a |-> ( ( b )
or ( (!b & !c)[*1:$] ##1 b ) )

This assumes b can occur in the next cycle after a and c is ignored.