Assertion signal (a) and signal (b)

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Hi Ben,
Still getting some failures with valid a and b.
a2 - EDA Playground

Did not follow the third assertion

ap_no3q_ab: assert property(@(posedge clk) not(a[*3] ##1 a[->1] intersect b[->1]));

Thanks,
JeffD