Assertion signal (a) and signal (b)

SystemVerilog
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2

In reply to dvuvmsv:


ap_a2b: assert property( @(posedge clk) a |-> ##[2:5] b);  
  // 2. signal (a) can be asserted 3 times consecutively before signal b asserts,
  // Before signal (a) assert 4th time, signal (b) should assert at least once
// Meaning, difference in the number of signal (a) and signal (b) should not exceed 3.
  ap_3athenb: assert property(@(posedge clk) a[*1:3] |-> b);  
  // Not a, aa, or aaa then another a and a&&b 
  ap_no3q_ab: assert property(@(posedge clk) not(a[*3] ##1 a[->1] intersect b[->1]));

I believe that your first “a” should be $rose(a) or an “a” ended with a “start”.
Let me know if this works for you.
Ben Cohen
Ben@systemverilog.us
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