Hi, Kindly help on this Assertion Question we want RESET should be high for the first 3 clock ticks of our simulation and then it should predominantly stay zero.

IMPORTANT NOTICE: Please be advised that the Verification Academy Forums will be offline for scheduled maintenance on Sunday, November 9th at 1:00 AM US/Pacific.

Verification Academy

Assertion Question

SystemVerilog

ronankilakshmi November 26, 2023, 10:49pm 3

Hello,
what does this mean in the above assertion property, #=#
Please assist.