In reply to ben@SystemVerilog.us:
I was also suggested the following that also works.
Edit code - EDA Playground // code
EPWave Waveform Viewer // wave
ap_sig1_2b: assert property(@(posedge clk)
$rose(sig1) |-> (sig1[*] intersect sig2[=1]) ##1 !sig1)
pass=pass+8; else fail=fail+8;
initial begin