Assertion Question

SystemVerilog
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5

In reply to Ashmika:

signal2 can only be high for one clock cycle

I am assuming you expect sig2 to be high on only 1 posedge of clock .On next posedge Sig2 should be low .

Since you are interested in checking Sig2 only when Sig1 is high :


property  prop ;
  @(posedge clk)
   $rose(sig2) && sig1 |=> $fell( sig2 ) ;
 endproperty

EDIT : Both Sig1 and Sig2 could be asserted on same posedge hence :


property  prop ;
  @(posedge clk)
   first_match( ( $rose(sig2) && sig1 ) or ( $rose(sig2) && $rose(sig1) ) ) |=> $fell( sig2 ) ;
 endproperty