In reply to ben@SystemVerilog.us:
Hi Ben,
Sorry for disturbing you again. I have a few questions and a few doubts.
- Why are we considering having ack and vld as a mistake?
ap_ack_vld: assert property(@(posedge clk) not($rose(ack) && vld)) else err3=err3+1;
If both of them are becoming 1 at the same clk-cycle , we can discard the idea of vld signal getting toggled or consider that vld got changed but we won’t count it because the question says between these two signals. So simply ignore edge ones. Why is it necessary then?
2)In the first two properties you have used goto operator for $changed(vld)[->1].What is the need of this ? you could have written vld && $changed(vld) . They mean same here , as we are checking for 1 clk-cycle.
3)Third doubt is regarding continuous repetition.The condition you have used
((vld && $changed(vld)[->1],count++)[*1:$] ##0 (count >= 2)
// or
first_match((vld && $changed(vld)[->1],count++)[*1:$] ##0 (count >= 2))
(vld && $changed(vld),count++) - this condition may or may not be continuous. So, why did you use * instead of = or → ?
4)The following is my solution. My logic was to check if vld!=$past(vld) and then count++. This operation will happen non-consecutive way. Now in the next cycle when the ack signal will go high, we’ll check if the count>=10 or not. Another thing I added to it. When the ack is rising along with checking the count I am also displaying the count which is not getting executed. Don’t know why?
$rose(req) |=> ((vld != $past(vld),count++)[->0:$] ##1 ($rose(ack),$display("count is:%0d and time is:%0t",count,$realtime))) ##0 (count >= 2);
- Is it not satisfying the requirement? If not then I would like to know why? Where I am getting it wrong?