Assertion ,properties, and sequences

SystemVerilog
,
1

I am new to systemVerilog. I read the following:
https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/

In the following code (under Properties and Sequences )
sequence request
Req;
endsequence

sequence acknowledge
##[1:2] Ack;
endsequence

property handshake;
@(posedge Clock) request |-> acknowledge;
endproperty

assert property (handshake);

I do not fully understand what ## stand for, and what is the meaning of property in systemVerilog.

2

In reply to saritr:

stands for clock cycle delay. In this case ##[1:2] stands for either 1 or 2 clock cycle delays. In systemverilog property defines a behavior of design. In this case you are checking the behavior of the design that it is asserting acknowledge signal within the specific clock cycle delay after request.