In reply to bhj78:
In reply to ben@SystemVerilog.us:
Hi Ben ,
I mean to say
Are you saying that for every occurrence of “a” then variable b occurs after 50 clock cycles?
No, we are only concerned about the last occurrence of “a”.I mean after last occurrence of “a”
Or, are you saying that if I have something like:
a[*3] ##1 !a then b after the last b? Not this
Pehaps something like: $rose(a) ##1 !a[->1] |-> ##50 b;
but something like
a[*3] ##1 !a then b after the last a? this but here a is getting repeated n number of times at any interval as it is randomised so
Pehaps something like: $rose(a) ##1 !a[->1] |-> ##50 b;// donot know this will catch the last occurance of a
a will be asserted within 50 cycles. if a is not asserted within 50 cycles , then b should be asserted. Should we consider that a will be the last occurrence?
always@(posedge clk) begin
if(a) count <= 0 ;
else count <= count + 1 ;
end
assert property(@ posedge clk count >= 50 |-> b)
is there case there in signal a can be asserted after 50 clock cycles?