Assertion on req and gnt signals

In reply to ben@SystemVerilog.us:

Hi Ben,

Suppose there is another spec that says the following : -
1)There should be single gnt pulse for every req pulse made.
2)gnt can come between 1 to 100 clock cycle.
3)Its also possible that there can be another req pulse before the gnt of previous req pulse was completed (For example at time 0 there was req pulse and at time 3(say) there is another req pulse (till now there is no gnt for previous req pulses) so now if gnt comes it ,the following assertion would pass : -
req |-> ##[1:100] gnt.

One corner case scenario would be : - 10 req pulse came with single gnt (on say 11th cycle) but rest of the 9 gnts didn’t came.

Awaiting your reponse ben.

Thanks