In reply to pk_94:
// req forllowed by 2 grants
ap_req_grant_grant: assert property(@ (posedge clk)
$rose(req) |=> grant[->2] );
// No req until after the 2nd grant
// a grant cannot occur in the same cycle as req
ap_grant_noreq_grant: assert property(@ (posedge clk)
$rose(grant) |-> !req[*1:$] ##1 grant );
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy