Assertion Issue - After Reset

SystemVerilog
1

Guys,

I have an assertion for the signal which get its initial value after reset and should not change throughout simulation.

disable (reset) (multi_factor) |-> $stable(multi_factor);

But, I’m getting assertion failure on reset, since it is initialized at the same clock.

Is below is right?

disable (reset) (multi_factor) |=> $stable(multi_factor);

req_length should not change as long as req_valid is high and until req_ready is high.

disable (reset) $rose(req_valid) |-> $stable(req_length)[*0:$] ##1 $rose(req_ready);

I tried…

disable (reset) $rose(req_valid) |=> $stable(req_length)[*0:$] ##1 $rose(req_ready);

disable (reset) $rose(req_valid) |=> $stable(req_length)[*1:$] ##1 $rose(req_ready);

but did not work.

Note: req_length, res_length and multi_factor are intergers.

And,

I have another question about “cover property”.

How do we avoid the “fake” pass?

If property did not start (antecedence fails) , coverage would be pass/fail?

And one more…

basic question.

What is the difference between property and sequence? I know that property has “implication” and sequence doesnt.

See my example below…

property p1;
reqA |-> resA;
endproperty
assert p1;

sequence s1;
reqA ##0 resA;
endsequence
assert s1;

property p2;
reqB |=> resB;
endproperty
assert p2;

sequence s2;
reqB ##1 resB;
endsequence
assert s2;

Please clarify.

John

2

Hello,

you could try below options to disable assertion while reset


   (multi_factor & (!reset) |-> $stable(multi_factor);

Also there is also way to disable all concurrent assertion in moulde/interface/program(Section 16.15 1800-2012 LRM)


   default disable iff reset;

Regards,
Vinay Jain

3

In reply to Vinay Jain:

Vinay,

Thanks for your comment.

But, Issue is not disabling the assertion on reset.

disable iff (reset) (multi_factor) |-> $stable(multi_factor);

Requirement:
after reset, multi_factor is assigned to new value and that new value should not change in the whole simulaiton.

Issue is, after reset assertion is active and at the same clock cycle comparing the multi_factor value with previous clock cycle value. previous clock cycle value is X or some random value. Assertion failed on that cycle. Later no issue.

How to avoid that?

Below statement helps, but is that right?

disable iff (reset) (multi_factor) |=> $stable(multi_factor);

all,

And also I may need some answers for the other questions as well.

John