In reply to ben@SystemVerilog.us:
the requirement is like below:
Signal A can be high n clk cycles (n :0,1,2…1000000000000000)
after each 10clk cycle A remains high , I wan to check 5 clk cycle past value of B at end of that sequence.
For example :
A is high from 3rd clk to 19 clk
So I wan to check value of B at clk ---- 8th -----------------------after end of 12th clk cycle
Similarly : B at clk -----9th ------------------------------after 13th clk cycle
B at clk -----10th ------------------------------after 14th clk cycle
B at clk -----11th ------------------------------after 15th clk cycle
B at clk -----12th ------------------------------after 16th clk cycle
B at clk -----13th ------------------------------after 17th clk cycle
B at clk -----14th ------------------------------after 18th clk cycle
B at clk -----15th ------------------------------after 19th clk cycle
No check at 16th ------------------------------after 20th clk cycle
Is it clear ?
an it be done like beolw:
property se;
@(posedge clk)
A[*10] |- $past(B,5);
endproperty