Assertion in system verilog

SystemVerilog
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4

In reply to skumarsamal:

You need to define your requirements for things like "what happens if A[*10] fails? At what point do you start counting the sequence and exclude the other sequences. An English definition would help you write the assertions. I made some assumptions about your intent, and wrote the following, but you need to refine this code to meet your requirements.

module tenclk;
// $rose(A) ##0 A[*10] |-> $past(B,5) 
// But I wan also to slide that window for next subsequent 10 
// repeatative match for A without any $rose of A.
    bit clk, go=1'b1, A, B; 
    function void set_go();  go=1'b1; endfunction 
    function void reset_go();  go=1'b0; endfunction
    sequence q_ten; @ (posedge clk) (A && go, reset_go()) ##0 (A)[*10]; endsequence 
    
    ap_set_go_if_not_10: assert property(@ (posedge clk) A && go |-> 
              A[*10]) else set_go(); 
    
    ap_AB: assert property(@ (posedge clk) q_10.triggered |-> ($past(B, 5), set_go())); 
    
endmodule