Assertion in system verilog

In reply to ben@SystemVerilog.us:

But I wan also to slide that window for next subsequent 10 repeatative match for A without any $rose of A .

Will it possible ?

like:
clk: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A: 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
B: 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0

I am expecting comparision starts from clk : 11 and end at 21 continuously , with past 5 clk cycle from current value of B .