Ex:
clk : 1 2 3 4 5 6 7 8 9 10 11 12 13
A : 0 0 1 1 1 1 1 1 1 1 1 1 1
B :our issue is tah 0 0 0 0 0 1 1 1 1 0 0 0
mean I wan to check 5 clk cycle past value of ‘B’ on 10th consucatave true of A.
I am doing like below:
A[*10] → $past(B,5)
But it’s not working as expected ., can anyone pls suggest correct one?
Your issue is that at every successful attempt of A you start a new assertion thread. You need to restrict the first successful attempt. Thus,
Ex:
clk : 1 2 3 4 5 6 7 8 9 10 11 12 13
A : 0 0 1 1 1 1 1 1 1 1 1 1 1
B : 0 0 0 0 0 1 1 1 1 0 0 0
$rose(A) ##0 A[*10] |-> $past(B,5)
Ben Cohen http://www.systemverilog.us/
- SystemVerilog Assertions Handbook, 3rd Edition, 2013
- A Pragmatic Approach to VMM Adoption
- Using PSL/SUGAR … 2nd Edition
- Real Chip Design and Verification
- Cmpt Design by Example
- VHDL books