In reply to ben@SystemVerilog.us:
I have two intrefaces because each one of them “describe” different block in the design.
Can you give me example hot to do it in one of the interfaces?
In reply to ben@SystemVerilog.us:
I have two intrefaces because each one of them “describe” different block in the design.
Can you give me example hot to do it in one of the interfaces?