In reply to saritr:
In reply to ben@SystemVerilog.us:
Is there any way to do it from one of the interface?
Yes, assertions can be instantiated in modules, interfaces, checkers (1800 checker), programs. However, you must access the variables used in the assertions.
You declared 2 separate interfaces. If that is a requirement, then, you could in one of those interfaces, create an instance of the other interface. However, Why can’t you have just ONE interface, why do you really need TWO? If one interface, then all the variables used in the assertion are directly accessible from within the interface. Obviously, the assertion will only fire when the interface is instantiated somewhere. Thus,
interface tx_if (input bit clk, input bit tx_srstn);
//dut input
logic [15:0] xi;
logic [15:0] xq;
logic [15:0] sin;
logic [15:0] cos;
int chind2;
//dut output
logic [15:0] y;
// NOT sure if you need to type cast the sqrt. If so, then
typedef logic [15:0] WORD;
// I want to check that every time sin equal to 1(decimal) y will be xi/sqrt(2),
always if(sin==4'H0001)
a_sin: assert(y == WORD'(xi/(2 ** 0.5)) );
// see 1800'2012 11.4.3 Arithmetic operators
//and every time cos equal to 1(dec) y will be xq/sqrt(2)
always if(cos==4'H0001)
a_cos: assert(y == WORD'(xq /(2 ** 0.5)) );
endinterface