Assertion for parameterized module instances

SystemVerilog
,
3

In reply to dave_59:

Thank you Dave, below code you shared(one correction != 10), worked better than mine,

module exp #(WIDTH=10) (input bit a);
  initial begin
    $display("WIDTH = %d",WIDTH);
  end
 //this is a generate-if
 if (WIDTH != 10) $fatal(0,"Width != 10");
endmodule : exp

Further, I did not understood one thing here,

// this is a generate-if
if (WIDTH == 10) $fatal(0,“Width != 10”);

What do you mean by this? when we keep outside of initial begin , is that generate-if ? how that works ? do you have some good link which I can refer for both localparams and generate.