Assertion for parameterized module instances

SystemVerilog
,
2

In reply to megamind:

Seems very strange to declare a parameter and not allow it to be overwritten—that is their whole point. There is a localparam construct that cannot be overwritten.

But if you really have some reason to code you parameter this way, you can use the $fatal system task to end the simulation as the action block of your assertion, to you can use a generate block $fatal to end at elaboration.

module exp #(WIDTH=10) (input bit a);
  initial begin
    $display("WIDTH = %d",WIDTH);
  end
// this is a generate-if
 if (WIDTH == 10) $fatal(0,"Width != 10");
endmodule : exp