In reply to ben@SystemVerilog.us:
revisit:
found sync_accept_on might be able to solve my issue.
property seq1101_to_det;
@(posedge clk) sync_accept(detected) sequence_in ##1 sequence_in ##1 !sequence_in ##1 sequence_in |=> detected;
endproperty
upon detected assertion, sequence detector fsm would return to initial stage, so it’s safe to kill current thread and make it vacuous I think