Assertion for invalid clock behavior with respect to clock request and acknowledge

SystemVerilog
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4

In reply to ChChee:

I wanted to screen the condition below (missing ack=1) in a sequence of:

  1. clk off && req=1 && ack=0
  2. clk active && req=1 && ack=0
  3. clk off && req=1 && ack=0