In reply to ben@SystemVerilog.us:
I wanted to write a simple set of basic checks. This checker is intended to contain the loss of sop, eop, val, violation of the minimum and maximum length of the packet, and, if necessary, the loss of ipg. You are probably right, this approach is conceptually wrong and will not be able to cover all requirements. But unfortunately I don’t have a verification team, and I’m a FPGA developer, so I often have to use simple solutions for mediocre verification)
Specifically in this case, I have a very large design containing many IPs, including PHYs and other network modules. For testing, I wrote a package generator that sends packages to the project and compares them at the output. Globally, this allows you to understand that an error has occurred in the project, but in which specific place - not. To determine in which particular place, you really need to draw up a verification plan and do some serious work. But I don’t have skills and time for that) Therefore, I add such primitive checks to some nodes.