Assertion for check between signals changing on different edges of same clock

SystemVerilog
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6

In reply to verif4life:

Two options:

  1. you can use ##1 delay to avoid the first clocking event.

ap_arbiter: assert property(first_match(@(negedge clk) ##1 $fell (a)) |-> (@(posedge clk) $fell (b)))
2) Use tasks recommended by Ben.
https://verificationacademy.com/forums/systemverilog/paper-understanding-sva-engine-simple-alternate-solutions

For casting, It is always better to do typecast first.