In reply to rag123:
Thanks for your reply. It is working.
Can you provide a way so that it does not throw an error for the first clock edge??
Here the clock starts after power on reset so cannot use disable iff (rst)… and default value of signal is x and sampled value at first clocking event is 0. So $fell will be true and hence the antecedent…
Also cannot change signal ‘a’ to bit type because it is an internal DUT signal… is it good way to take variable in assertion interface as bit type so that it would be automatically typecast x, z to 0???