Assertion for check between signals changing on different edges of same clock

SystemVerilog
, ,
4

Try this (Haven’t tested)


//  There are 2 signals a, b. Signal a is synchronous to negedge of clk and Signal b synchronous to posedge of clk.
//Whenever signal a falls at a negedge of clk, at the immediate following posedge of clk,signal b should fall.
//clk is same for a, b.

 ap_arbiter: assert property(first_match(@(negedge clk) $fell (a)) |-> (@(posedge clk) $fell (b)))
            $display ("Assertion passed",$time);
            else $display ("Assertion failed",$time);