In reply to ben@SystemVerilog.us:
I tried your assertion but the value of b doesn’t change when offset becomes 0. Is there anyway I can find the change of b and check for signal a. I tried the below code too but it said illegal operand for constant expression
property delay_assert(a,offset,b);
@(posedge clk) disable iff(reset)
$changed(b) |-> ($past(a,offset)==1);
endproperty