In reply to ben@SystemVerilog.us:
Hi,
Thank you very much for your reply. I am sorry if my requirements were not clear. b is a signal which contains values incrementing from 0 to 10 and keeps repeating for the entire time. When the value of signal b changes, at that point signal a which is 1 bit should rise before an offset. rise of signal a should happen before every start time of values changing in signal b by an offset.