Assertion for a signal to rise before an offset

ben2 · February 24, 2019, 5:32pm

Requiremens In my assertion, an offset should determine how much earlier to send a signal prior to a signal with value incrementing in every clock cycle.

That requirement is ambiguous. Do you mean to say:
Following the rise of signal “a”, the 32-bit signal “b” should be incremented after an offset of a number of system clocks. The value of that offset is stored in an 8-bit register. During that offset time, signal “a” shall remain in the logical high state.
With the above requirements, I would write:


property delay_assert(a,offset,b);
 bit[7:0] v_offset; 
 bit[[31:0] v_b;  
 @(posedge clk) disable iff(reset)
 ($rose(a), v_offset= offset, v_b=b) |-> 
   first_match((a,v_offset=v_offset - 1'b1)[*0:$] ##1 v_offset==0) ##0 
   $changed(b) && b==v_b+1'b1);
endproperty

I understand that you hastily wrote your requirements for the assertion for this forum. However, requirements really need to be better defined. For your benefit and this audience, I recommend that you take a look at my book (below) that goes ito great details about defining requirements and verification plans.
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