In reply to ben@SystemVerilog.us:
Hi,
The requirement is very clear. I want to check X only. t1, t2 are not clock timings and they are random timings but the assertion should be written with respect to clock and Iam checking for a functionality.
In reply to ben@SystemVerilog.us:
Hi,
The requirement is very clear. I want to check X only. t1, t2 are not clock timings and they are random timings but the assertion should be written with respect to clock and Iam checking for a functionality.