Lots of issues with you assertion:
- Your requirements are not clear. From your first statement about requirements, it is strange to see “X” as a requirement! signals are true or false. If you don’t care about the value, then you can use true for a clock delay. But to require that a signal be an X is unusual; sounds kind of meaningless. Also, when you state t1, t2, etc, you seem to imply a single clock, and all signals (a and b) synchronous to that clock. That is not what you expressed in the assertion.
2)Use to test for an X. $isunknown(expression) returns `true (bit 1’b1) if any bit of the expression is X or Z. This is equivalent to ^(expression) === ’bx. - I can help you with this assertion if ou write in English your requirements.
Ben SystemVerilog.us