In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for your reply. When I run your suggested code, though I get pass occurrences (4 times), I still get the violations (486).
“assert_macros.sv”, 187: .REGMODE_CHECK8: started at 57943712000fs failed at 58022120000fs
Offending ‘repeat or delay’
“assert_macros.sv”, 187: .REGMODE_CHECK8: started at 57792242000fs failed at 58022120000fs
Offending ‘repeat or delay’
“assert_macros.sv”, 187: .REGMODE_CHECK8: started at 57729872000fs failed at 58022120000fs
Actually my objective is to check the addr1 - addr0 = 40’h5000 only for the first time when Line Count becomes 1->2 combined with first rising edge of AWVALID and AWREADY. I don’t need to check throughout. Also, it can’t be given in number of fixed clock cycles as CLOCK freq varies b/w 550 MHz and 600 MHz at which operation is happening. Please suggest. Thanks.