In reply to ben@SystemVerilog.us:
Another approach to solve this not quite correct assertions:
a |-> ##[0:$] b |-> c; // cannot succeed
a |-> b[->1] |-> c; // OK
a |-> b[->1] ##0 c; // OK, my preference
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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