[Assertion] Dynamic Repetition

SystemVerilog
5

In reply to ben@SystemVerilog.us:
Thanks Ben.

This is the long way for a small fix and I doubt the reusability.

However, the assertion works fine after reusing the dynamic repetition sequence from your package example and modifying a sequence and a property as below.


  // Reused Your sequence for dynamic repetition
  sequence q1_rpt_simple_range_q2(sequence q1, int range, sequence q2); 
      int v, diff;
      (1,  diff=range)  ##0  
      first_match((diff>0 ##0 q1, diff=diff-1'b1) [*1:$] ##1 q2 );
  endsequence

  // Modified the sequence and property
  // CFG3: positive level of B
  sequence CFG3_s;
    int count;
    // Older code
    //($rose(B),count=0) ##0 (count<delay(CFG3),count+=1)[*] ##1 (count==delay(CFG3)) && $fell(B);
    // Modified as
    ($rose(B),count=0) ##0 (count<delay(CFG3),count+=1)[*] ##0 (count==delay(CFG3)) && B;
  endsequence // CFG3_s
 
  // Property to check A -> B -> C transition
  property P1;
    // Older code
    //@(posedge CLK) CFG1_s |-> ##1 CFG2_s ##0 CFG3_s ##0 CFG2_s ##0 CFG3_s ##0 CFG2_s(1);
    // Modified as
    @(posedge CLK) CFG1_s |-> ##1 q1_rpt_simple_range_q2((CFG2_s ##0 CFG3_s),(CFG5-1),CFG2_s(1));
  endproperty // P1