In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for reply.
I have a common clk for all 3 signals(a,b,c) of same module.
My requirement is that signal a repeats for 3 times but not for every clk then i need to wait for delay of value b then c signal should start risiong from 0 to 1.
The signal a sample on posedge clk but repetition of signal a is not dependent on clk. the second/ occurance of signal a may happen after more no of clks(ex: 4/5/6). basically we should not be dependent on clk while checking signalfor repetition.
I have written something like this: But it results in below compilation Error.
Can you please correct me if iam doing some thing wrong.
Expected specification terminator “;”.
property a_b_c_timing;
@(posedge clk)
@(posedge a)
(a[*4]) #b |-> $rose(c)
endproperty
assert_a_b_c_timing_chk: assert property(a_b_c_timing)
Thanks,
Murali