Assertion check for a signal which depends on 2 other signals

SystemVerilog
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In reply to muralidar:
Your requirements are ambiguous; the following comments may help you in clarifying your requirements.

  1. I have 3 signals a,b,c which are asynchronous.
    [Ben] So they are not derived from any clock? Do you mean that a, b, c are generated from different clocks or are they derived from flops going through combinational signals? Could they be glitchy?

  2. a signal changes 4 times for a operation i.e i need to calculate time for 4 pulses of a
    [Ben] you did not state that your assertion needs to calculate “time”. ???

  3. b has some default value which i can use direct value.
    [Ben] what does the default value has to do with your assertion? Is it fixed all the time, or does it change. How does “b” play in your requirements?

  4. [quote]c signal should start after 4 pulses of a + .Ho w can i write assertion check for the signal C that is dependent on a and b.I see write a separate a sequence for calculating the signal a change for 4 times, and then use that sequence inside a property to check the c condition.

[Ben]SVA needs clocks or events. If you want to say that after 4 pulses of “a”, then if(b) then c changes, then you can do something like the following, but you need clocks or you need to generate events.


// assuming that a, b, c are generated from separate clocks
module t; 
  bit clka, clkb, clkc;
  bit a, b, c; // single pulses 
  bit go; // to start the checking process. More on that after you clarify your requirements 
  ap_abc: assert property(@(posedge clka) go && a ##1 a[->3] 
                        |-> @(posedge clkb)  b[->1] ##0 @(posedge clkc) c[->1]);
 endmodule

GBGO; clarify what you requirements and the clocking scheme.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us