In reply to Tudor Timi:
Embedding assertions in comments still has the same issues I mentioned above, namely potential for errors, time stamping and unnecessary re-synthesis, and supporting assertion code not intended for synthesis.
It is the responsibility of management (or project engineer) to enforce the methodologies used in the project.
Just because an engineer does not “like” the binding concept is not a reason for not using assertions.
The benefits of assertions were proven because they not only clarify the requirements and assumptions, they also pinpoint the errors quickly.
SVA and PSL are just an assertion language used for verification. One can also write assertions in plain RTL-like code, since an assertion is simply a statement that some property of the design is true.
As far as PSL or SVA, SVA is far superior. Engineers who use VHDL must (or most likely) know SystemVerilog.
Personally, I would abandon VHDL and use SystemVerilog for RTL and verification.
Ben http://SystemVerilog.us