In reply to bharat_vg:
As the assertions are evaluated in the preponed reason. So whenever there is posedge of ref_clk , means that at the same time clkA will rise ,Hence the value just before the rise of clkA is taken to be ZERO (everytime) as it remains high for only half cycle w.r.t ref_clk .So antecedent would never meet.
This assertion would vacuously pass.