[Assertion] Assertion to validate clock signals are in the required order

SystemVerilog
, ,
8

In reply to Sri52:

In reply to pk_94:
SO this assertion needs a reference clock to ensure the relationship between the two clocks ?

If we use ref_clk as suggested here, then we can write following assertion to check that WHEN clkA asserts THEN in next ref_clk cycle clkB asserts and clkA is not high.


assign ref_clk = clkA | clkB;
property clk_a_then_b;
    @(posedge ref_clk)
    $rose(clkA) |-> ##1 ($rose(clkB) && ~clkA);
endproperty

I am not sure if this is the correct solution for your question though.