Assertion - Accesing signals of a .vhdl file from .sv file

SystemVerilog
1

Hello All,

I would like to write assertions for a VHDL RTL, so my intention is

abc.vhdl (Top VHDL file , all port mapping of sub blocks are done here)
wrap.sv (instantiates the abc.vhdl file, this will be used by my verif environ)
int_rest (internal signal in abc.vhdl , this does not reach the IO of abc.vhdl)

Now my intention is to write system verilog assertions on the internal signal ‘int_rest’, so i would like to access this internal signal from the wrap.sv (where all my assertions will sit).

Please assist me in achieving this.

Maximus

2

You need to use the SystemVerilog bind command that inserts a SV module with assertions inside a VHDL entity. If you are using Questa, look in the user guide for the section Using SystemVerilog bind Construct in Mixed-
Language Designs

3

You have few choices:

  1. As Dave said, use SV bind feature - and bind it to entity-architecture pair, that way your SV can see internal signals too. Below is a single slide from our SVA-VHDL training that we recently delivered to a customer who had similar requirement.

  1. You can use VHDL-2008 “extern” signal feature to bring internal signals to a top level VHDL and use. Also see: http://verificationacademy.com/forum/verification-methodology-discussion-forum/systemverilog-and-other-languages-forum/20411-question-related-sv-binding

  2. PSL is now part of VHDL and hence one could potentially stay within VHDL and achieve all of these - if desired.

HTH
Ajeetha, CVC