Assert(std::randomize(variable))

SystemVerilog
,
1

Hello,
Could you please let me know what simulators should do when we use
assert(std::randomize(variable))
and assertions are turned off

I am using it but bit confused what should simulators do ?
will it still randomize variable
or keep previous value
or it is going to be 0 (variable is int)

Thanks

2

The LRM just says that $assertoffshall stop the checking of all specified assertions. The LRM does not specifically mention if the evaluation of expression is inseparable from its checking. Apparently, most simulators ignore the entire assertion statement when the assertion is turned off. This has the unfortunate consequence of not calling the randomize method.

We recommend using a simple if ( randomize() ) statement to avoid this issue as well as having an assert statement in your testbench interferes with the reporting of functional coverage of your design.

3

In reply to dave_59:

For performance reasons, it is logical to ignore the assertion entirely when turned off.

4

In reply to shalom:

per a recommendation from my Co-author Srinivasan Venkataramanan,

// assert(req.randomize()); // ** AVOID THIS 
if (!req.randomize()) `uvm_error("USER_DEFINED_FLAG", "This is a randomize error");

//req is a class handle in the above example

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115